Search for: All records

As femtosecond (fs) laser machining advances from micro/nanoscale to macroscale, approaches capable of machining macroscale geometries that sustain micro/nanoscale precisions are in great demand. In this research, an fs laser sharp shaping approach was developed to address two key challenges in macroscale machining (i.e. defects on edges and tapered sidewalls). The evolution of edge sharpness (edge transition width) and sidewall tapers were systematically investigated through which the dilemma of simultaneously achieving sharp edges and vertical sidewalls were addressed. Through decreasing the angle of incidence (AOI) from 0° to −5°, the edge transition width could be reduced to below 10µm but at the cost of increased sidewall tapers. Furthermore, by analyzing lateral and vertical ablation behaviors, a parameter-compensation strategy was developed by gradually decreasing the scanning diameters along depth and using optimal laser powers to produce non-tapered sidewalls. The fs laser ablation behaviors were precisely controlled and coordinated to optimize the parameter compensations in general manufacturing applications. The AOI control together with the parameter compensation provides a versatile solution to simultaneously achieve vertical sidewalls as well as sharp edges of entrances and exits for geometries of different shapes and dimensions. Both mm-scale diameters and depths were realized with dimensional precisions below 10µm and surface roughness below 1µm. This research establishes a novel strategy to finely control the fs laser machining process, enabling the fs laser applications in macroscale machining with micro/nanoscale precisions.

 

Silicon carbide (SiC) MOSFET power modules are being used for high power applications because of their superior thermal characteristics and high blocking voltage capabilities over traditional silicon power modules. This paper explores modeling the thermal process of a SiC MOSFET power module through a high-order finite element analysis (FEA) based thermal model and then reducing the order of the FEA thermal model using a Krylov subspace method. The low-order thermal model has a significantly reduced computation cost compared to the FEA model while preserving the accuracy of the model. The proposed method is applied to generate low-order thermal models for a SiC MOSFET, which are validated by computer simulations with respect to the FEA thermal model.